Method and system for generating test pulses to test electronic elements

ABSTRACT

A method and system for generating test pulses to test electronic elements are disclosed. After determining a transmission clock, which is smaller than a test clock, and a serial of predetermined pulses, the serial of data bits corresponding to the serial of predetermined pulses can be generated. Then the serial of data bits can be transformed into a serial data stream for transmission. By transmitting the serial data stream according to the transmission clock, the serial of predetermined pulses corresponding to the test clock can be generated.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a method and system forgenerating test pulses, and more particularly to a method and system forprogrammable generating test pulses.

2. Description of the Prior Art

As is known, tests on electronic element such as IC (integrated circuit)could be categorized into the following three types, direct currentparametric test, dynamic functional test, and alternating current test.Among these three types, dynamic functional test is more complicated andimportant than other tests. In order to perform dynamic functional testof an electronic element, it is required to have a driver for generatingtest pulses to drive the electronic element, a comparator for examiningthe output pulses of the electronic element, and a power supply forgenerating stable currency. Test pulses generated by the driver are sentinto an electronic element to be tested. The electronic element to betested is driven by these test pulses and produces correspondent outputpulses, which would be received and examined by the comparator. At theend, the comparator would compare the received output pulses with aserial of predetermined pulses to determine the functional test resultof the tested electronic element.

In this regard, test pulses are different for adapting to the differentelectronic element to be tested. It means that the driver for generatingtest pulses is also required to change for varied electronic elements.Since the test pulses for an electronic element are usually quitecomplicated and the differences of test pulses for different electronicelements are quite significant, the driver is needed to be customizedfor each electronic element. Therefore most of customized drivers aremade of ASIC (Application Specified Integrated Circuit) that consumeslots of costs and time to design before test. Besides, the customizeddrivers are not reusable for other test cases.

Generally speaking, the input and output signals of an electronicelement are called pulses, which have three measurable elements, timeduration, voltage, and represented logical data, respectively. As shownin FIG. 1A, signal 10 is a serial of continuous pulses, which could beinterpreted as a combination of a logical data 1 and a logical data 0.Logical data 1 and 0 may be represented by a correspondent highervoltage, VH, and a correspondent lower voltage, VL, respectively.Logical data may be represented in other alternative ways. For examplelogical data 1 could be represented by a signal bounce from VL to VH.The entire duration of the logical data 1 is T1; the voltage is raisedfrom VL to VH after duration T2 from the beginning; and then the voltageis further returned to VL after duration T3.

Signals, which are produced by a typical clock generator (TG), havefixed periods. A main clock (MC) with a period Tl is designated as thebasis of the logical data 1. A fist clock (C1) has the same period of MCis delayed for a duration of T2. Similarly, a second clock (C2) also hasthe same period as MC is delayed fro a duration of T2+T3. Both of C1 andC2 are produced by applying different delay lines on signals of MC. Inorder to generate a pulse such as logical data 1, it is required tocombine a pattern signal (P), MC, C1, and C2. The pattern signal (P) isused to provide a combination of VH and VL.

In the consequence, as shown in FIG. 1B, a typical driver comprises aclock generator (TG), a pattern generator (PG), a programmable dataselector (PDS), a format controller (FC), and a voltage input (VI).Timing clock sequences such as above-mentioned MC, C1, and C2 aregenerated by the clock generator. Varied patterns could be generated bythe pattern generator and be further directed to designated paths by theprogrammable data selector. At last, pulses are modulated by the formatcontroller and are amplified in an appropriate range of voltage by thevoltage input.

To summarize, the generation of test pulses is to combine the timingclock sequences from the TG with the patterns from the PG by the formatcontroller. And the delay lines are also required to produce variedtiming clock sequences. Moreover, the working clock of the electronicelement goes higher, and the delayed duration of delay line goes shorterin contrary. However, for the test on high frequency electronic elementssuch as radio frequency (RF) communication chips, the delay duration ofdigital delay line may not be short enough to fulfill the requirement oftest. Instead, it requires analog delay lines to produce qualified shortdelay duration. Most drivers are made of ASIC that could provide merelysome certain fixed timing clock sequences. Because different testelectronic elements are generated from different patterns, thesepatterns should be generated from varied timing clock sequences thatASIC drivers could not provide. For current test apparatus on highfrequency electronic elements, the shortcomings include high costs, lackof reusability, and the need of excess analog logics. It is desired tohave a new method and system for solving these mentioned shortcomings toreduce costs and increase test performance.

SUMMARY OF THE INVENTION

One improvement against the shortcomings mentioned above, a method andsystem for generating high frequency test pulses without applying analogdelay lines is disclosed in accordance with the present invention.

Besides, another improvement of the present invention is the disclosureof a method and system for programmable and reusable generating highfrequency test pulses.

According to these mentioned improvements, a method for generating testpulses to test electronic elements is disclosed in accordance with thepresent invention. In this case, a transmission clock, a test clockwhich has a smaller frequency than the transmission clock, and a serialof predetermined pulses corresponding to the test clock are determined,and a serial of data bits would be generated according to the serial ofpredetermined pulses and the transmission clock. Furthermore, a serialdata stream could be transformed from the series of data bits. At last,a serial of test pulses could be derived from the serial of data streamand the test clock.

In this regard, the present invention discloses a system for generatingtest pulses to test electronic elements, which comprises a clockgenerator, a storage unit, a transformation unit, and a transmissionunit. At first, the transmission clock and the test clock (which has asmaller frequency than the transmission clock) generated by the clockgenerator are dispatched to the transmission unit and the electronicelement, respectively. Secondly, the serial of data stream correspondingto the transmission clock could be transformed by the transformationunit from the serial of data bits stored in the storage unit. Finally, aserial of test pulses corresponding to the test clock could be derivedby the transmission unit from the serial of data stream corresponding tothe transmission clock.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings incorporated in and forming a part of thespecification illustrate several aspects of the present invention, andtogether with the description serve to explain the principles of theinvention. In the drawings:

FIG. 1A shows a diagram illustrating major components of pulses;

FIG. 1B depicts a block diagram illustrating high level functions of theprior art;

FIG. 2A shows a flowchart diagram in accordance with a preferredembodiment of the invention;

FIG. 2B shows an output diagram in accordance with a preferredembodiment of the invention; and

FIG. 3 shows a functional block diagram in accordance with a preferredembodiment of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

Having summarized various aspects of the present invention, referencewill now be made in detail to the description of the invention asillustrated in the drawings. While the invention will be described inconnection with these drawings, there is no intent to limit it to theembodiment or embodiments disclosed therein. On the contrary the intentis to cover all alternatives, modifications and equivalents includedwithin the spirit and scope of the invention as defined by the appendedclaims.

It is noted that the drawings presented herein have been provided toillustrate certain features and aspects of embodiments of the invention.It will be appreciated from the description provided herein that avariety of alternative embodiments and implementations may be realized,consistent with the scope and spirit of the present invention.

It is also noted that the drawings presented herein are not consistentwith the same scale. Some scales of some components are not proportionalto the scales of other components in order to provide comprehensivedescriptions and emphases to this present invention.

A high frequency signal transmission serializer disclosed in accordancewith the present invention is capable to transmit a serial of highfrequency signals for derivation of test pulses. In this regard, aserial of high frequency signals derived from a serial of data bitscould be transmitted by the serializer. Hence different serials of databits could be provided corresponding to different test pulses. Itincreases the reusability of test apparatus and does not need analogdelay lines to test high frequency electronic elements in the prior art.

The functional test on electronic element is to drive the electronicelement by a serial of test pulses corresponding to the test clock. Theserial of test pulses could be generated from the test pattern of theelectronic element and the test clock of the test pattern. Therefore,the functional test result of the electronic element could be determinedby the serial of output pulses. In this regard, a method for generatingtest pulses to test electronic element in accordance with a preferredembodiment of the invention is shown in FIG. 2A. At first, atransmission clock is determined at step 210 from the test clock of theelectronic element. In the meanwhile, the frequency of transmissionclock should be a multiplier of the frequency of test clock. In otherwords, the test clock is synchronized to the transmission clock in thesame multiplier of period. For example, in case the period of the testclock is 100 ns (nanosecond) and the period of the transmission clock is5 ns, it takes one period for the test clock and 20 periods of thetransmission clock in the same duration at test. It is also applicablefor the transmission clock whose period is shorter than one nanosecondin accordance with the preferred embodiment of the invention. Theshorter period of transmission clock means a higher frequency of testpulses and the more precise control on the serial of test pulses.

Next step is shown at step 220, to generate multiple serials of databits corresponding to the serials of predetermined pulses 22 and thetransmission clock. As shown in FIG. 2B, the desired serial ofpredetermined pulses contains a combination of logical data 1s and 0s isgenerated corresponding to a test clock TC 1. Each pulse representing alogical data 1 or 0 is consisted by several sub-pulses in the serial ofsub-pulses 24 corresponding to the transmission clock. Since thesub-pulse maintains fixed voltage during its entire period, a serial ofdata bits can be interpreted from the logical data represented by thevoltage of these sub-pulses. For example, the length ratio of periodsbetween the test clock TC1 and the transmission clock TC2 is 8 to 1;therefore a pulse of the serial of predetermined pulses 22 is consistedof 8 sub-pulses in the serial of sub-pulses 24. Since each of thesub-pulses represents a logical data 1 or 0, a logical data 1 pulse ofthe serial of predetermined pulses 22 could be generated from acombination of eight sub-pulses representing logical data bits as“00111100”. Similarly, a logical data 0 pulse of the serial ofpredetermined pulses 22 could be generated from a combination of eightsub-pulses representing logical data bits as “11000011”. The serial ofdata bits 26 corresponding to the serial of predetermined pulses 22could be generated by the logical data represented by the sub-pulses.For example, the serial of data bits 26 represents the logical data 1and 0 corresponding to the serial of predetermined pulses 22 could bedenoted as “00111100” and “11000011”. In other words, a sub-pulserepresenting a data bit is sent in per period of the transmission clock.The voltage of the sub-pulse is determined by the value of the data bitand maintained during its period. Hence a serial of predetermined pulsescould be denoted by a serial of data bits.

Next, as shown in step 230, multiple parallel data streams are generatedby interleaving the bits of the serial of data bits to these multipleparallel data stream equally in order. For example, to transmit aplurality of bits through multiple paths, or to transmit a plurality ofbits to multiple storage units of a storage media (e.g. registers,buffers, and memory), the plurality of bits could be interleaved tothese paths or storage units in order as multiple parallel data streams.

Referring to step 240, a serial of data bits could be restored in orderfrom the interleaved multiple parallel data streams in the previousstep. At last, the serial of data bits is pre-emphasized and transmittedto the electronic element to be tested as shown in step 250. A sub-pulsecorresponding to a bit of the serial of data bits is generated in aperiod of said transmission clock; and the sub-pulse maintains thevoltage representing the logical data of correspondent bit value duringthe period.

Besides, the information of the serial of data bits is stored inmultiple paths or storage units at step 230 and 240 before the serial ofdata bits is formed. It becomes possible to transmit the serial of databits via a lower frequency logics or circuits by a serializer that worksat a higher frequency. Since it is easier for the pulses to attenuateand have loss in power in transmission at higher frequency oftransmission clock, to pre-emphasize the pulses before transmissioncould reduce the problems of attenuation and loss.

Referring to FIG. 3, in accordance with a preferred embodiment of thepresent invention, a system for generating test pulses to testelectronic element is disclosed. The system for generating test pulsescomprises a clock generator 41, a storage unit 42, a transformation unit43, and a transmission unit 44.

According to the description of step 210, a transmission clock 412 isdetermined from the test clock 414 of the electronic element 45 to betested. Next, a serial of data bits 422 corresponding to thetransmission clock 412 is determined from the desired serial ofpredetermined pulses 444. In this regard, the test clock 414 and thetransmission clock 412 are both generated by the clock generator 41; theserial of data bits 422 is stored in the storage unit 42. As what isdescribed in step 230 and step 240, a serial data stream 442 istransformed by the transformation unit 43 from the serial of data bits422. Finally, the transmission unit 44 transmits the serial data stream442 in the form of the serial of predetermined pulses corresponding totransmission clock 412 to the electronic element 45.

The transformation unit 43 and the transmission unit 44 are used totransmit the serial data stream 442 corresponding to the transmissionclock 412. The functionalities performed by the transformation unit 43and the transmission unit 44 could be done by a serializer, too. Thefunction of a serializer is to transmit serial data stream in higherfrequency from the received parallel data streams in lower frequency.Moreover, this embodiment of the present invention could furthercomprise a data bits generation unit. Therefore the serial ofpredetermined pulses could be inputted into the data bits generationunit in other formats (e.g. programming languages or text data) and theserial of data bits could be generated according to the test clock andthe transmission clock.

In accordance with one preferred embodiment of the present invention, aprogrammable latch array with serializers for generating test pulses totest electronic elements is disclosed. The programmable latch array withserializers comprises a storage unit, a serializer, a clock generator,and a logic circuit for the performance of the programmable latch array.In this regard, the serial of data bits could be stored in the storageunit; it could also be transmitted by the serializer in the transmissionclock. The clock generator and the transmission unit could beimplemented inside the programmable latch array or be provided from theexternal logic circuits. Furthermore, a data bits generation unit couldalso be implemented inside the programmable latch array.

The foregoing description is not intended to be exhaustive or to limitthe invention to the precise forms disclosed. Obvious modifications orvariations are possible in light of the above teachings. In this regard,the embodiment or embodiments discussed were chosen and described toprovide the best illustration of the principles of the invention and itspractical application to thereby enable one of ordinary skill in the artto utilize the invention in various embodiments and with variousmodifications as are suited to the particular use contemplated. All suchmodifications and variations are within the scope of the inventions asdetermined by the appended claims when interpreted in accordance withthe breadth to which they are fairly and legally entitled.

1. A method for generating test pulses to test an electronic element,comprising: determining a transmission clock, a serial of predeterminedpulses, and a test clock corresponding to the serial of predeterminedpulses, wherein said serial of predetermined pulses are sent to saidelectronic element and the frequency of said transmission clock ishigher than the frequency of said test clock; generating a plurality ofserial data bits, wherein said serial data bits are generated from saidserial of predetermined pulses and said transmission clock; transformingsaid serial data bits into a serial data stream; and sending said serialdata stream to said electronic element, wherein said data stream istransmitted in a specific frequency to send a specific number of bitsfor forming said serial of predetermined pulses according to saidtransmission clock.
 2. The method of claim 1, wherein the frequency ofsaid transmission clock is a multiplier of the frequency of said testclock and said transmission clock is synchronized to said test clock inthe multiplier of the period.
 3. The method of claim 2, wherein saidserial of predetermined pulses comprises a plurality of pulses; and eachof them is generated by the corresponding bits of said serial of databits.
 4. The method of claim 3, wherein the number of the correspondentbits of said serial of data bits is said multiplier.
 5. The method ofclaim 1, wherein a sub-pulse corresponding to a bit of said serial ofdata bits is generated in a period of said transmission clock; and saidsub-pulse maintains the voltage representing the logical data ofcorrespondent bit value during said period.
 6. The method of claim 1,further comprising a pre-emphasized serial data stream, wherein thevoltage of said serial of predetermined pulses is regulated bypre-emphasizing before transmission.
 7. The method of claim 1, whereinsaid serial data stream is transformed from parallel data streams; saidparallel data streams are interleaved from said serial of data bits. 8.The method of claim 7, wherein the information of said serial of databits is interleaved to said parallel data streams in order.
 9. A systemfor generating test pulses to test an electronic element, comprising: aclock generator to generate a transmission clock and a test clock for anelectronic element, wherein the frequency of said transmission clockbeing higher than the frequency of said test clock; a storage unit tostore a serial of data bits, wherein said serial of data bits beinggenerated from a serial of predetermined pulses and said transmissionclock; a transformation unit, wherein said serial of data bits beingretrieved from said storage unit and transformed into a serial datastream by said transformation unit; and a transmission unit to transmitsaid serial data stream, wherein said serial of predetermined pulsesbeing generated according to the fixed number of bits of said serialdata stream in the fixed frequency of said transmission clock.
 10. Thesystem of claim 9, wherein the frequency of said transmission clock is amultiplier of the frequency of said test clock and said transmissionclock is synchronized to said test clock in the multiplier of theperiod.
 11. The system of claim 10, wherein said serial of predeterminedpulses comprises a plurality of pulses; and each of them is generated bythe corresponding bits of said serial of data bits.
 12. The system ofclaim 11, wherein the number of the correspondent bits of said serial ofdata bits is said multiplier.
 13. The system of claim 9, wherein asub-pulse corresponding to a bit of said serial of data bits isgenerated in a period of said transmission clock; and said sub-pulsemaintains the voltage representing the logical data of correspondent bitvalue during said period.
 14. The system of claim 13, wherein thevoltage representing the logical data of correspondent bit value of saidsub-pulse is regulated by pre-emphasizing before transmission.
 15. Thesystem of claim 9, wherein said serial data stream is transformed fromparallel data streams; said parallel data streams are interleaved fromsaid serial of data bits.
 16. The system of claim 15, wherein theinformation of said serial of data bits is interleaved to said paralleldata streams in order.
 17. A programmable latch array with serializerfor generating test pulses to test an electronic element, comprising: anapparatus comprising a programmable latch array with a serializer forgenerating a test clock and a transmission clock to said electronicelement and said serializer, respectively, and for storage of a serialof data bits which is generated from said transmission clock and aserial of predetermined pulses corresponding to said test clock, whereinthe frequency of said transmission clock being higher than the frequencyof said test clock; and a transformation unit, wherein said serial ofdata bits retrieved by said transformation unit being transmitted bysaid serializer, and said serial of predetermined pulses being generatedaccording to the fixed number of bits of said serial of data bits in thefixed frequency of said transmission clock.
 18. A programmable latcharray with serializer for generating test pulses to test an electronicelement of claim 17, wherein the frequency of said transmission clock isa multiplier of the frequency of said test clock and said transmissionclock is synchronized to said test clock in the multiplier of theperiod.
 19. A programmable latch array with serializer for generatingtest pulses to test an electronic element of claim 18, wherein saidserial of predetermined pulses comprises a plurality of pulses; and eachof them is generated by the corresponding bits of said serial of databits.
 20. A programmable latch array with serializer for generating testpulses to test an electronic element of claim 19, wherein the number ofthe correspondent bits of said serial of data bits is said multiplier.21. A programmable latch array with serializer for generating testpulses to test an electronic element of claim 19, wherein a sub-pulsecorresponding to a bit of said serial of data bits is generated in aperiod of said transmission clock; and said sub-pulse maintains thevoltage representing the logical data of correspondent bit value duringsaid period.
 22. A programmable latch array with serializer forgenerating test pulses to test an electronic element of claim 21,wherein the voltage representing the logical data of correspondent bitvalue of said sub-pulse is regulated by pre-emphasizing beforetransmission.